History
Arteris was founded in 2004 by Philippe Boucard and two other engineering executives who had worked together at T.Sqware, a startup that was acquired by Globespan.[7][8][9] Company executives wished to address problems with existing monolithic bus and crossbar interconnect technologies, such as wire and routing congestion, increased heat and power consumption, failed timing closure, and increased die area.[4][10] The firm’s leadership sought and received venture capital totaling $44.1 million for the creation of its new technology from investors, including ARM Holdings, Crescendo Ventures, DoCoMo Capital, Qualcomm, Synopsys, TVM Capital, and Ventech.[11][12]
By 2006, Arteris developed the first commercially available NoC IP product, called NoC Solution, followed in 2009 by a more advanced product, FlexNoC.[4][13][14] The products used “packetization and a distributed network of small interconnect elements to address congestion, timing, power and performance issues.”[4][15] Arteris marketed FlexNoC as an improvement on traditional SoCs interconnect fabrics, citing its reduction in gate count by 30 percent, reduction of wires by 50 percent, and a more compact chip floor as compared to a functionally equivalent hybrid bus or crossbar.[2][10][16]
Designers of SoCs began to take advantage of the technology’s increased design efficiency, flexibility, and a significant reduction in production costs.[16][17][18][19] By 2012, the company had over 40 semiconductor customers, including Qualcomm, Samsung, Texas Instruments, Toshiba, and LG Electronics, with 200 million SoCs being produced with Arteris IP.[4][20]
In October 2013, Qualcomm Technologies, Inc. acquired the FlexNoC network-on-chip product portfolio, but Arteris retained existing customer contracts and to continue licensing FlexNoC and modifying the source code for customer support. Qualcomm will provide engineering deliverables for the FlexNoC product line and updates to Arteris. Qualcomm does not maintain any ownership interest in Arteris.[21][22]
In September 2014, Arteris launched the Arteris FlexNoC Resilience Package, which added functional safety mechanisms to the FlexNoC interconnect IP useful for ISO 26262 and IEC 61508 standards compliance.[23]
In May 2016, Arteris released its first version of the Ncore cache coherent interconnect IP product with optional support for functional safety.[24]
Arteris presented the Ncore cache coherent interconnect IP version 3 and the optional Ncore Resilience Package for functional safety at the Linley Processor Conference in October 2017.[25]
In 2020, Arteris acquired Magillem Design Services, adding a suite of IP-XACT-based products for automating the creation of systems-on-chip and their associated software and firmware, verification and simulation platforms, and specifications and customer documentation.[26][27]
In 2021, Arteris announced the pricing of its initial public offering (IPO), listing under Nasdaq:AIP.[28][29]
In 2023, Arteris acquired Semifore, a provider of Hardware-Software Interface technology, to accelerate system-on-chip development and integration automation.[30]
Also in 2023, Arteris launched FlexNoC 5 physically aware network-on-chip (NoC) interconnect IP. FlexNoC 5 enables SoC architecture teams, logic designers and integrators to incorporate physical constraint management across power, performance and area (PPA) to deliver a physically aware IP connecting the SoC. This technology enables 5X faster physical convergence over manual refinements with fewer iterations from the layout team for automotive, communications, consumer electronics, enterprise computing, and industrial applications.
In 2024, Arteris released the latest version of Ncore cache coherent interconnect IP. The latest release of Ncore works with multiple processor IPs, including RISC-V and the next-generation Armv9 Cortex processor IP. Ncore boasts multi-protocol support, allowing seamless integration of IPs connected to the same NoC fabric. Designers can choose from CHI-E, CHI-B and ACE fully coherent agent interfaces and ACE-Lite IO-coherent interfaces. AXI is also supported for interfacing with sub-systems or devices without coherency requirements. These capabilities enhance the flexibility and adaptability of Ncore, making it an ideal solution for complex and evolving SoC designs, including safety-critical applications.
In 2025, Arteris launched FlexGen, a revolutionary, smart NoC interconnect IP. With up to a 10x productivity boost, FlexGen slashes design iterations, significantly reducing the time required to develop cutting-edge chips. It also achieves up to a 30% reduction in wire length to lower power use, and up to 10% reduction in latency that results in improved performance in SoC and chiplet designs.
In 2026, Arteris closed the acquisition of Cycuity, a provider of semiconductor cybersecurity assurance technology. By combining system IP from Arteris with silicon hardware security assurance technology from Cycuity, the acquisition positions Arteris to address growing concerns around hardware security.[31]
As of February 2026, its technology has shipped in more than 4 billion devices, signifying important growth in enabling the underlying data movement for AI-era chips and chiplets.[32]
